The present invention relates to a semiconductor device having pattern regions requiring a polishing process and a method for manufacturing the same.
Recently, the needs for high capacity semiconductor memory devices have grown. This is especially true for dynamic random access memory (DRAM). However, due to the limitation in increasing a chip size, an increase in DRAM capacity also reaches a limitation. The increase of a chip size reduces the number of chips per wafer, which causes a reduction in the productivity of devices. Therefore, many efforts have been made to reduce a cell area by modifying a cell layout and integrate more memory cells into a single wafer. Due to such efforts, the cell structure is changing from an 8F2 layout to a 6F2 layout.
Also, as semiconductor fabrication technologies have been developed, planarization technologies have also been advanced. In the conventional art, a traditional borophosphosilicate glass (BPSG) reflow has been used to planarize an interlayer dielectric film. In recent years, however, improvement in the degree of planarization has been achieved by applying a chemical mechanical polishing (CMP) process.
The application of a CMP process has improved the degree of planarization to some extent, but has limitations in obtaining uniform heights inside a chip.
That is, due to the different pattern density in a cell region and a core/peripheral circuit region, the degree of polishing at an insulating film differs from the cell region to the core/peripheral circuit region. This causes a dishing phenomenon where an upper portion of the core/peripheral region is recessed.
FIGS. 1a to 1c are cross-sectional views illustrating a general method for manufacturing a semiconductor device including a CMP dummy pattern.
Referring to FIG. 1a, a cell region and a core/peripheral circuit region defined in a substrate 10 have a very different pattern density. As illustrated in FIG. 1b, if a CMP process is performed on an insulating film 20 deposited over the substrate 10, a dishing phenomenon occurs. This is caused by a wide interval between patterns in the core/peripheral circuit region, resulting in a dish shaped recess.
If a layer is deposited over the dished insulating film in a subsequent process, an optical focus mismatch can occur due to the height difference caused by the dishing, which results in pattern failure.
To prevent the dishing phenomenon, a wafer open control dummy pattern, as a CMP dummy pattern, is formed in the core/peripheral circuit region. That is, as illustrated in FIG. 1c, the dishing phenomenon could be overcome because the interval between patterns is substantially reduced by forming a wafer open control dummy pattern 15 in an unused empty space of the core/peripheral circuit region.
As such, since the CMP process is sensitive to the pattern density, it is important to design the semiconductor device to maintain uniform pattern density inside the chip in a design step.
However, in the case of a semiconductor device having a 6F2 layout, ISO patterns formed in the cell region are arranged obliquely in a diagonal direction, whereas isolation (ISO) patterns formed in the core/peripheral circuit region are arranged vertically with respect to a word line in the same manner as the 8F2 layout. Thus, as can be seen from the measurement result of FIG. 2, the warpage of the wafer after the ISO process becomes different according to the position of the wafer. If the warpage of the wafer is not uniform, a misalignment may be caused by etching residues when cell patterns are formed after the ISO process. Particularly, in forming a flash memory floating gate (FG), the etching residues may cause a greater problem.
To solve these shortcomings, if a pattern of the core/peripheral circuit region and a pattern of the cell region are formed similar to each other, the warpage of the wafer may be improved to some extent. However, in the actual design step, it is difficult to modify the pattern of the core/peripheral circuit region to be equal to the pattern of the cell region.